1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device, specifically to a manufacturing method of a semiconductor device having a through-hole electrode.
2. Description of the Related Art
A CSP (Chip Size Package) has received attention in recent years as a three-dimensional mounting technology as well as a new packaging technology. The CSP means a small package having about the same outside dimensions as those of a semiconductor die packaged in it.
A BGA type semiconductor device with a through-hole electrode has been known as a kind of CSP. This BGA type semiconductor device has a through-hole electrode that penetrates through a semiconductor substrate and is connected with a pad electrode. And a plurality of ball-shaped conductive terminals made of metal such as solder is arrayed in a grid pattern on a back surface of the semiconductor device.
When the semiconductor device is incorporated into electronic equipment, each of the conductive terminals is connected to a wiring pattern on a circuit board such as a printed circuit board.
Such a BGA type semiconductor device has advantages in providing a large number of conductive terminals and in reducing size over other CSP type semiconductor devices such as an SOP (Small Outline Package) and a QFP (Quad Flat Package) that have lead pins protruding from their sides.
Next, a conventional manufacturing method of the BGA type semiconductor device with the though-hole electrode will be described referring to the drawings. FIGS. 24 and 25 are cross-sectional views showing such a conventional manufacturing method of the semiconductor device.
First, a semiconductor substrate 70 having a pad electrode 71 formed on its top surface through an interlayer insulation film 72, that is a first insulation layer, is provided as shown in FIG. 24. Next, a supporting body 73 is bonded to the top surface of the semiconductor substrate 70 through a resin layer 74, when necessary. Then a mask pattern (not shown) is formed on a back surface of the semiconductor substrate 70 and the semiconductor substrate 70 is etched to form a via hole 76 that is cut through the semiconductor substrate 70 from a position of the back surface corresponding to the pad electrode 71 to the top surface. A portion of the interlayer insulation film 72 exposed on a bottom of the via hole 76 is removed by etching. Next, an insulation film 77, that is a second insulation film, is formed on the back surface of the semiconductor substrate 70 and on a surface of the via hole 76.
And the insulation film 77 on the bottom of the via hole 76 is etched off by reactive ion etching to expose the pad electrode 71, as shown in FIG. 25. Then a through-hole electrode (not shown) that is connected with the pad electrode 71 is formed in the via hole 76. And a wiring layer (not shown) connected with the through-hole electrode is formed on the back surface of the semiconductor substrate 70. Furthermore, a protection layer (not shown) is formed over the back surface of the semiconductor substrate 70 and the wiring layer. Then a portion of the protection layer is removed to expose a portion of the wiring layer, and a conductive terminal (not shown) is formed on the portion of the wiring layer. After that, the semiconductor substrate 70 is separated into a plurality of semiconductor dice by dicing.
When the insulation film 77 is formed by CVD (Chemical Vapor Deposition) in the above-described manufacturing method of the semiconductor device, a supply of a gas of film-forming materials is insufficient at the bottom of the via hole 76. Therefore, the insulation film 77 at the bottom of the via hole 76 is formed to have a thickness thinner than that of the insulation film 77 on the back surface of the semiconductor substrate 70.
Thus, taking advantage of the difference in the film thicknesses described above, the insulation film 77 at the bottom of the via hole 76 is removed by etching without using a mask in the process step to expose the pad electrode 71 by reactive ion etching of the insulation film 77 on the bottom of the via hole 76. The insulation film 77 at the bottom of the via hole 76 is etched off to expose the pad electrode 71 before the insulation film 77 on the back surface of the semiconductor substrate 70 is etched off. The etching described above must be controlled so that the pad electrode 71 is exposed while the insulation film 77 is left on a side wall of the via hole 76.
Further description on the technologies mentioned above is disclosed in Japanese Patent Application Publication No. 2003-309221, for example.
In the etching process of the insulation film 77 at the bottom of the via hole 76 by the reactive ion etching, however, electric field is converged on the insulation film 77 at corners 70a and 70b of the via hole 76 in the semiconductor substrate 70 as shown in FIG. 25, making concentration of the reactive ions there higher than at other locations. As a result, there is a possibility that the etching of the insulation film 77 is accelerated at the corners 70a and 70b to make the film thickness extremely thin or remove the insulation film 77 completely.
Also, there is a tendency that the insulation film 77 formed on the side wall of the via hole 76 other than at the corners 70a and 70b is removed by the etching to reduce the thickness. Therefore, when the through-hole electrode (not shown) is formed in the via hole 76 after the etching, insulation failure is caused between the through-hole electrode and the semiconductor substrate 70 in some cases. As a result, reliability and yield of the semiconductor device have been reduced.